The present invention relates generally to integrated circuits. More particularly, the present invention relates to an improved apparatus and method for providing a phase locked loop clock divider circuit that utilizes a high speed programmable linear feedback shift register.
The use of linear feedback shift registers is well known in integrated circuit technology. Linear feedback shift registers may be used in a number of applications. For example, a linear feedback shift register may be used to implement a clock divider circuit. A clock divider circuit is used to divide a master clock signal to obtain a different frequency clock signal.
In a phase locked loop (PLL) circuit, a clock divider circuit located within the feedback path needs to run at the frequency of the voltage controlled oscillator (VCO) in the PLL. The function of the PLL clock divider circuit in the feedback path is to divide the VCO frequency by a programmable value N (referred to as the xe2x80x9cregister valuexe2x80x9d). Division of the VCO frequency by the register value N provides an input to the phase detector within an analog core of the PLL. This causes a closed loop to be formed within the PLL. Clock divider circuits in the feedback path of a PLL are typically binary based counters or linear feedback shift register (LFSR) based counters.
High frequency PLL circuits have voltage controlled oscillators (VCO) that operate at very high frequencies. This, in turn, requires that the clock divider circuit in the feedback path of the PLL must also operate at very high frequencies. Prior art high frequency PLL circuits that have high frequency VCO output typically use custom designed binary counters or LFSR based counters in the feedback path that typically operate in the range of 250 MHz to 500 MHz. LFSR based counters operate at a relatively higher frequency compared to custom designed binary counters. To make prior art LFSR based counters to operate at frequencies greater than 500 MHz, the timing critical LFSR feedback path must have not more than one logic gate.
It would be desirable to have a high frequency PLL circuit having an LFSR based counter as a clock divider in a feedback path that would operate efficiently at frequencies greater than 500 MHz.
It would also be desirable to have a high frequency PLL circuit having an LFSR based counter as a clock divider in its feedback path with a shorter critical timing path than prior art LFSR based counters.
It would also be desirable to have a high frequency PLL circuit having an LFSR based counter as a clock divider in its feedback path having only one logic gate present in the critical timing path of the LFSR based counter.
The present invention is directed to an apparatus and method for providing a phase locked loop clock divider circuit that utilizes a high speed programmable linear feedback shift register.
An advantageous embodiment of the present invention comprises a phase locked loop clock divider circuit that utilizes a high speed linear feedback shift register (LFSR). The LFSR of the present invention comprises a feedback path that is implemented as a one stage pipeline. The output R[4] of an LFSR4 unit is XNORed with the output R[3] of an LFSR3 unit of the LFSR counter of the present invention. The output R[3] and an inverted version of the output R[3] from the LFSR3 unit are provided to the inputs of a multiplexer that is present in the feedback path of the LFSR counter. The output R[4] from the LFSR4 unit is provided to the xe2x80x9cenablexe2x80x9d signal input line of the multiplexer.
It is an object of the present invention to provide an apparatus and method for providing a phase locked loop clock divider circuit that utilizes a high speed linear feedback shift register that does not need to employ as many logic gates in a timing critical feedback path as prior art linear feedback shift registers.
It is another object of the present invention to provide an apparatus and method for providing a phase locked loop clock divider circuit that utilizes a high speed linear feedback shift register that is capable of operating at high frequencies.
It is also an object of the present invention to provide an apparatus and method for providing a phase locked loop clock divider circuit that utilizes a high speed linear feedback shift register that is capable of operating at a faster rate than prior art linear feedback shift registers.
It is another object of the present invention to provide an apparatus and method for providing a phase locked loop clock divider circuit that utilizes a high speed linear feedback shift register having a scalable design that can implement an xe2x80x9cany bitxe2x80x9d clock divider having only two bits in its polynomial equation.
It is yet another object of the present invention to provide an apparatus and method for providing a phase locked loop clock divider circuit that utilizes a high speed linear feedback shift register that is capable of generating desired values of a clock divide signal by using non-timing critical pre-loading flip flop circuits.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the Detailed Description of the Invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject matter of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the Detailed Description of the Invention, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: The terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprisexe2x80x9d and derivatives thereof, mean inclusion without limitation, the term xe2x80x9corxe2x80x9d is inclusive, meaning xe2x80x9cand/orxe2x80x9d; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, to bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontroller,xe2x80x9d xe2x80x9cprocessor,xe2x80x9d or xe2x80x9capparatusxe2x80x9d means any device, system or part thereof that controls at least one operation. Such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document. Those of ordinary skill should understand that in many instances (if not in most instances), such definitions apply to prior, as well as future uses of such defined words and phrases.